Robust Nanowire Decoding

In recent years, a number of nanoscale devices have been demonstrated that act as wires and gates. In theory, these devices can interconnect to form general purpose architectures. Unfortunately, our ability to place individual devices is poor, and device reliability may be substantially lower than that of current CMOS technology. Nanoscale architectures must be designed with these limitations in mind. Designs must account for extremely high levels of variation in both device placement and operation. It remains uncertain exactly what these robust nanoscale architectures will look like. At a minimum, however, they will require control over individual nanoscale wires. A device which controls a set of parallel nanowires with a second set of input wires is called a nanowire decoder. In order to interface nanotechnology with existing lithographically produced technology, the decoder’s input wires can be large, mesoscale wires. In this paper we provide a general model for nanowire decoders. We use this model to give the conditions that the decoders must meet. We also describe how to create fault-tolerant decoders for use in both memories and circuits. Finally we discuss the overhead and testing procedures required to ensure that stochastically assembled decoders behave deterministically. The problems we address are very relevant to current research in nanoscale computing. They also highlight the more general issues of stochastic assembly and fault-tolerance. Both issues will likely remain a fundamental characteristic nanoscale computing, and as such become a primary focus of the budding field of computational nanotechnology.